Prof. Vojin G. Oklobdzija
  ACSEL Director
  info [at] acsel-lab.com
 

Presentations
1982-1989
1990-1994
1995-1999
2000 to now

Projects
Energy Efficient Circuits
High Performance Adder
Low Power IC Design
Low Power Clocking Project
Clocked Storage Elements
Books
on Fabrication
on Applications
on uProcessor Des.
on Clocking
on Comp. Eng.
on System Design

Conference Resources
Computer Arithmetic Proceedings
Conference Calls
Conferences of Interest
Misc. Topics
Press Releases
Expert Witness and Litigation Consulting
Technical Consulting
Sponsorship
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Presentations (since 1982)

  1. 1982 VLSI TECHNOLOGY. Electrical Engineering Department, University of Belgrade, Yugoslavia, September 18, 1982.
  2. 1982 TESTABILITY ENHANCEMENT OF VLSI USING CIRCUIT STRUCTURES. Presented at the ICCC '81 IEEE International Conference on Circuits and Computers, New York, NY, September 28 - October 1, 1982.
  3. 1983 IMPROVING TESTABILITY BY USING ADDITIONAL CIRCUITS. Presented at the Seventeenth Asilomar Conference on Circuits, Systems and Computers, Pacific Grove, CA, October 31 - November 2, 1983.
  4. 1984 ON TESTABILITY OF CVS LOGIC. Presented at IBM Internal Technical Liaison Symposium, La Grande, France, April 3-5, 1989.
  5. 1984 TEST GENERATION FOR FET SWITCHING CIRCUITS. Presented at the Internal Test Conference, Philadelphia, PA, October 16-18, 1984.
  6. 1984 ON TESTABILITY OF CMOS-DOMINO LOGIC. Presented at the 14th International Symposium on Fault Tolerant Computing, Orlando, FL, June 20-22, 1984.
  7. 1985 SOME OPTIMAL SCHEMES FOR ALU IMPLEMENTATION IN VLSI TECHNOLOGY. Presented at the 7th Symposium on Computer Arithmetic, Urbana, IL.
  8. 1985 DESIGN-PERFORMANCE TRADE-OFFS IN CMOS-DOMINO LOGIC. Presented at the Custom Integrated Circuits Conference, Portland, Or, May 22, 1985.
  9. 1986 ALGORITHM FOR IMPLEMENTATION OF A FAST AND OPTIMAL ALU IN VLSI TECHNOLOGY. Computer Science Department, University of California at Los Angeles, Los Angeles, California, February 18, 1986.
  10. 1986 DESIGN TRADE-OFFS IN VLSI TECHNOLOGY. Electrical Engineering Department, Columbia University, New York, N.Y., March 7, 1986.
  11. 1986 TESTABILITY OF DYNAMIC CMOS CIRCUITS. Fifth IEEE West Coast Workshop, Lake Tahoe, California, April 20-23, 1986.
  12. 1986 REDUCED INSTRUCTION SET ARCHITECTURES FOR VLSI IMPLEMENTATION. Electrical Engineering Department, University of Belgrade, Yugoslavia, September 9, 1986.
  13. 1987 SINGLE-CHIP ARCHITECTURE FOR REAL-TIME COMPUTATION OF THE WIGNER DISTRIBUTION OF ACOUSTIC SIGNALS. Presented at the 21st Asilomar Conference on Signals, Systems, and Computers, November 2-4, Pacific Grove.
  14. 1988 ARCHITECTURAL STUDY OF AN INTEGRATED FIXED AND FLOATING POINT VLSI-ASIC PROCESSOR. University of California Irvine, Irvine, California, March 23, 1988.
  15. 1988 EFFICIENT VLSI ALGORITHM FOR FAST ALU IMPLEMENTATION. Department of Computer Engineering, University of California, Santa Cruz, November 17, 1988.
  16. 1988 ARCHITECTURE FOR SINGLE-CHIP ASIC PROCESSOR WITH INTEGRATED FLOATING POINT UNIT. Presented at the 21st Hawaii International Conference on System Sciences, Kailua-Kona, Hawaii, January 5-7, 1988.
  17. 1988 ARCHITECTURAL STUDY FOR AN INTEGRATED FIXED AND FLOATING-POINT VLSI-ASIC PROCESSOR. Presented at COMPEURO-'88. Symposium on Circuits and Systems, Brussels, April 11-14, 1988.
  18. 1989 EFFICIENT VLSI IMPLEMENTATION OF ADDITION. University of San Diego, San Diego, California, February 23, 1989.
  19. 1989 801: A PERSPECTIVE ON IBM RISC. Electrical Engineering Department, Stanford University, California, April 19, 1989.
  20. 1989 PERSPECTIVE ON RISC ARCHITECTURE. Monterey Institute of Technology, Queretaro, Mexico, July 10, 1989.
  21. 1989 RECENT DEVELOPMENTS IN VLSI TECHNOLOGY, CONCITEQ. Technology Institute of the State of Queretaro, Queretaro, Mexico, July 17, 1989.
  22. 1989 STUDY OF FAST ADDER IMPLEMENTATIONS. Electrical Engineering Department Seminar, Stanford University, California, December 13, 1989.

    23. 1990 to 1994
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  23. 1991 EVOLUTION OF RISC INTO SUPER-SCALAR ARCHITECTURE AND A LOOK BEYOND. Computer Sciences Department Seminar, Columbia University, February 20, 1991.
  24. 1991 ISSUES IN RISC AND SUPER-SCALAR ARCHITECTURE . Electrical Engineering Department Seminar, Princeton University, April 16, 1991.
  25. 1991 SUPER-SCALAR ARCHITECTURE AND BEYOND. NEC Corporate Research Center Seminar, Princeton New Jersey, April 17, 1991.
  26. 1991 ADVANCES IN CONTEMPORARY RISC ARCHITECTURE. 1991 Belgrade Summer School on Modern Computer Architecture, Short Course, Sava Congress Center, May 8-9, 1991.
  27. 1991 PERSPECTIVE ON SIMD ARCHITECTURES AND APPLICATIONS. Advanced Computer Research Institute Seminar, ACRI Lyon FRANCE, May 14, 1991.
  28. 1991 PROGRAMAS PARA ENSENAR COMPUTACION EN UNIVERSIDADES. Short Course (in Spanish), Asemblea de Rectores, Lima PERU, sponsored by Fulbright program, September 10-13, 1991.
  29. 1991 TEMAS AVANZADAS DE LA ARQUITECTURA DE COMPUTADORES. Short Course (in Spanish ), Asemblea de Rectores, Lima PERU, sponsored by Fulbright program, September 16-19, 1991.
  30. 1991 REDES DE COMPUTADORAS. Short Course (in Spanish), Asemblea de Rectores, Lima PERU, sponsored by Fulbright program, September 23-26, 1991.
  31. 1991 PLANO POR DESARROLLO DE REDES LOCALES EN UNIVESIDADES. Seminar (in Spanish) , Universidad Nacional de Ingenieria, Lima PERU, sponsored by Fulbright program, September 18, 1991.
  32. 1991 PLANIFICACION Y DESARROLLO DE COMPUTATORAS EN UN AMBIENTE ACADEMICO. Seminar (in Spanish), Pontifica Universidad Catolica del Peru, Lima PERU, sponsored by Fulbright program, September 25, 1991.
  33. 1991 PERSPECTIVAS POR DESARROLLO DE COMPUTACION EN UN PAIS DE TERCER MUNDO. Seminar (in Spanish), Universidad Mayor de San Marcos (the oldest university of Americas), Lima, PERU, September 26, 1991.
  34. 1992 ISSUES IN SUPER-SCALAR ARCHITECTURE: Pipelining and Contention Resolution, Invited Talk, Centre for Signal Processing Research, Space Centre for Satelite Navigation, Queensland University of Technology, Brisbaine, Australia, May 18th, 1992.
  35. 1992 SIMD MACHINES: IBM's GF-11, Seminar, Department of Electronic Engineering, La Trobe University, Melbourne, Australia, May 25, 1992.
  36. 1992 RECONFIGURABLE PROCESSOR FOR REAL-TIME SIGNAL ANALYSIS, Seminar, Department of Electronic Engineering, La Trobe University, Melbourne, Australia, May 26, 1992.
  37. 1992 PRINCIPLES OF RISC ARCHITECTURE AND THEIR INFLUENCE ON SUPER-SCALARS: A RISC PERSPECTIVE, Invited Talk, Melbourne University, Greenwood Lecture Theatre, Melbourne, Australia, May 27, 1992.
  38. 1992 ISSUES IN SUPER-SCALAR ARCHITECTURE: PIPELINING AND CONTENTION RESOLUTION, Invited Talk, CITRI - Commonwealth Information Technology Research Institute, Melbourne, Australia, May 27, 1992.
  39. 1992 ISSUES IN OPTIMIZING CACHE HIERARCHY FOR PERFORMANCE, Seminar, Department of Electronic Engineering, La Trobe University, Melbourne, Australia, May 28, 1992.
  40. 1992 PRINCIPLES OF RISC ARCHITECTURE AND THEIR INFLUENCE ON SUPER-SCALARS, Seminar, Department of Computer Sciences, University of Waikato, Hamilton, New Zealand, June 4, 1992.
  41. 1992 RESEARCH DIRECTIONS IN COMPUTER ENGINEERING, Seminar, Intel Corporation, Folsom, California, October 14, 1992.
  42. 1993 DEVELOPMENT OF COMPUTER ARITHMETIC ALGORITHMS AND MAPPING OF ALGORITHMS INTO TECHNOLOGY, Seminar, LSI Logic Corporation, Milpitas, California, January 22, 1993.
  43. 1993 EVOLUTION OF RISC INTO SUPER-SCALAR ARCHITECTURE: PERSPECTIVE ON RISC, IEEE Seminar at San Francisco State University, San Francisco, California, March 11, 1993.
  44. 1993 MULTIPLIER DESIGN UTILIZING IMPROVED COLUMN COMPRESSION TREE AND OPTIMIZED FINAL ADDER IN CMOS TECHNOLOGY, 10th Anniversary 1993 International Symposium on VLSI Technology, Systems and Applications, Taipei, TAIWAN, May 12-14, 1993.
  45. 1993 MULTIPLIER OPTIMIZATION IN CMOS TECHNOLOGY, Seminar, Toshiba ULSI Technology Center, Toshiba Corporation, Kawasaki, JAPAN, May 17, 1993.
  46. 1993 ISSUES IN SUPER-SCALAR ARCHITECTURE: PIPELINING AND CONTENTION RESOLUTION, Seminar, Department of Information Sciences, Kyoto University, Kyoto, JAPAN, May 20, 1993.
  47. 1993 MULTIPLIER SPEED OPTIMIZATION: IMPROVED COLUMN COMPRESSION ALGORITHM AND OPTIMIZATION OF THE FINAL ADDER, Seminar, Hitachi Ltd. Central Research Laboratory, Tokyo, JAPAN, May 21, 1993.
  48. 1993 MULTIPLIER DESIGN CONSIDERATIONS IN CMOS: USE OF IMPROVED COLUMN COMPRESSION TREE AND OPTIMIZED FINAL ADDER, Seminar, LSI Logic Corporation, Milpitas, California, June 16, 1993.
  49. 1993 HIGH-PERFORMANCE PROCESSOR DESIGN ISSUES: PIPELINE SELECTION AND MATCHING OF THE INSTRUCTION SET, Seminar, Hitachi America Ltd., Brisbane, California, June 25, 1993.
  50. 1993 DESIGNING A PARALLEL MULTIPLIER OPTIMIZED FOR SPEED, UCLA Computer Science Seminar, Department of Computer Sciences, UCLA, Los Angeles, California, July 23, 1993.
  51. 1993 HIGH-PERFORMANCE COMPUTER ARCHITECTURE: SUPER-SCALAR AND RISC, National University of Singapore, Department of Computer Science, September 15, 1993.
  52. 1993 A HIERARCHICAL AND MODULAR CIRCUIT IMPLEMENTING LEADING ZERO DETECTOR FOR A HIGH-PERFORMANCE FLOATING-POINT PROCESSOR, 5th International Symposium on IC Technology, Systems and Applications, ISIC-93, Nanyang Technological University, Singapore, September 16.
  53. 1993 RISC AND HIGH-PERFORMANCE SINGLE PROCESSOR ARCHITECTURES, Computer Science Seminar, University of Sains, Pulau-Pinang, Malaysia, Septermber 21, 1993.
  54. 1993 DIRECTIONS IN PARALLEL COMPUTER ARCHITECTURES, Computer Science Seminar, University of Sains, Pulau-Pinang, Malaysia, Septermber 23, 1993.
  55. 1993 CONTENTION RESOLUTION AND PIPELINE ISSUES IN SUPER-SCALAR ARCHITECTURES: IBM RS/6000, Computer Architecture Seminar, University of California, Davis, California, November 11.
  56. 1993 PRINCIPLES OF RISC ARCHITECTURE AND ITS EVOLUTION INTO SUPER-SCALARS: A RISC PERSPECTIVE, UNINET Video Conference Seminar, The University of Sydney, University of New South Wales, Monash University, University of Technology Sydney, Sydney, AUSTRALIA, December 14, 1993.
  57. 1993 SUPER-SCALAR ARCHITECUTURE ISSUES: INSTRUCTION PHILOSOPHY AND CONTENTION RESOLUTION IN THE IBM RS/6000, UNINET Video Conference Seminar, The University of Sydney, University of New South Wales, Monash University, University of Technology Sydney, Sydney, AUSTRALIA, December 16, 1993.
  58. 1994 TECHNOLOGY UNDER CONTROL: ETHICS AND RESPONSIBILITY OF AN ENGINEER, Society of Women in Engineering, School of Engineering, University of California, Davis, California, February 2, 1994.
  59. 1994 DEVELOPMENT OF RISC ARCHITECTURE: AN INSIDER'S UNORTHODOX PERSPECTIVE, IEEE Seminar, School of Engineering, University of California, Davis, California, February 23, 1994.
  60. 1994 A METHOD FOR GENERATION OF FAST PARALLEL MULTIPLIERS, Computer Engineering Seminar, Department of Electrical Engineering, University of California, Davis, California, May 17, 1994.
  61. 1994 A METHOD FOR GENERATION OF FAST PARALLEL MULTIPLIERS, Seminar, Research and Development Department, Hitachi America Ltd., Brisbane, California, May 27, 1994.
  62. 1994 ON TESTABILITY OF PASS-TRANSISTOR LOGIC, Seminar, Research and Development Department, Hitachi America Ltd., Brisbane, California, May 27, 1994.
  63. 1994 AN ECL GATE FOR HIGH-SPEED AND LOW-POWER LOGIC IN BICOMOS PROCESS. Presented at the High Speed Electronics Research Department, AT&T Bell Laboratories, Homdel, New Jersey, July 21st, 1994.
  64. 1994 ADIABATIC CIRCUITS FOR LOW POWER COMPUTATION. Electrical Engineering Department, Imperial College, London, England, July 26th, 1994.
  65. 1994 ADIABATIC LOGIC AND LOW ENERGY COMPUTATION. Seminar at NEC USA C&C Research Laboratories, Princeton, New Jersey, August 10, 1994.
  66. 1994 USE OF ADIABATIC LOGIC FOR LOW ENERGY COMPUTATION. Seminar. Department of Electrical Engineering, Princeton University, August 10, 1994.
  67. 1994 PROGRESS IN DEVELOPMENT OF ADIABATIC CIRCUITS AND LOGIC. Seminar, VLSI Research Department, AT&T Bell Laboratories, August 19, 1994.
  68. 1994 THE OUTLOOK FOR DEVELOPMENT OF COMPUTING AND DIGITAL SYSTEMS IN THE NEXT DECADE. Invited Distinguished Lecture, Department of Electrical Engineering, University of Belgrade, Yugoslavia, September 26, 1994.
  69. 1994 LOGIC SYNTHESIS FOR ASIC. Invited Lecture, Institute of Automation, Chinese Academy of Science, Beijing, P. R. of China, October 18, 1994.
  70. 1994 DEVELOPMENT AND SYNTHESIS OF DUAL VALVE LOGIC USING PASS TRANSISTOR DESIGN TECHNIQUE. Invited Lecture, Insititute of Microelectronics, Chinese Academy of Science, Beijing, P. R. of China, October 18, 1994.
  71. 1994 LOGIC SYNTHESIS USING GUIDED ALGORITHMIC APPROACH. Invited Lecture, Department of Electrical Engineering, Tsinghua University, Beijing, P. R. of China, October 19, 1994.
  72. 1994 LOGIC SYNTHESIS FOR ASIC: A GUIDED ALGORITHMIC APPROACH. First International Conference on ASIC, Fragrant Hill, Beijing, P. R. of China, October 20, 1994.
  73. 1994 SYSTEM FOR RAPID PROTOTYPING OF APPLICATION SPECIFIC SIGNAL PROCESSORS FOR ASIC IMPLEMENTATION. First International Conference of ASIC, Fragrant Hill, Beijing, P. R. of China, October 20, 1994.
  74. 1994 A METHOD FOR GENERATION OF SPEED OPTIMIZED PARALLEL MULTIPLIER. Special Seminar, Hitachi Central Research Laboratory, Kokubunji, Tokyo, JAPAN, October 24, 1994.

    75. 1995 to 1999
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  75. 1995 Performance Issues in Super-Scalar RISC Processors: Value of Register Renaming Algorithm, Seminar at San Francisco State University, San Francisco, California, March 11, 1995.
  76. 1995 RE-ENGINERIA DE SISTEMAS DE INFORMACION PARA LOS ANOS 90, 1st International Conference on System Engineering, Lima, PERU, June 1st, 1995 (in Spanish).
  77. 1995 SISTEMAS DE INFORMACION: ARQUITECTURA DE SISTEMAS MODERNOS, 1st International Conference on System Engineering, Lima, PERU, June 1-2, 1995 (two day workshop in Spanish).
  78. 1995 OPTIMAL STRATEGIES FOR PARALLEL MULTIPLIER DESIGN, Electrical Engineering Department, University of Belgrade, Yugoslavia, July 28, 1995.
  79. 1995 New Differential Logic based on pass-Transistor design, Electrical Engineering Department, University of Belgrade, Yugoslavia, September 14, 1995.
  80. 1995 Algorithm and method for synthesis of fast parallel multiplier, Electrical Engineering Department, University of Belgrade, Yugoslavia, September 15, 1995.
  81. 1995 A PERSPECTIVE ON NEW GENERATION OF SUPER-SCALAR RISC PROCESSORS, Honywell-Bull Group User Seminar, Budva, Yugoslavia, September 21, 1995.
  82. 1995 New Differential Logic based on pass-Transistor design, Ecole Superieure d'Ingenieurs en Electrotechnique et Electronique, Noisy le Grand , FRANCE, September 26, 1995.
  83. 1996 ADVANCED LOGIC DESIGN: METHODOLOGY AND CIRCUIT TECHNIQUES, series of lectures, Hewlett-Packard Laboratories, Palo Alto , February-April, 1996
  84. 1996 ADVANCED LOGIC DESIGN: METHODOLOGY AND CIRCUIT TECHNIQUES, series of lectures, Fudan University, Shanghai , P.R. CHINA, April 22-26, 1996.
  85. 1996 LA HISTORIA DEL DESARROYO DE SYSTEMAS DE COMPUTACION Y LA PROYECTION POR EL FUTURO, Universidad San Francisco Xavier de Chuquisaca , Sucre, BOLIVIA, September 24, 1996.
  86. 1997 MODERN MICROPROCESSOR ARCHITECTURES, Intel Corporation, Beaverton, Oregon, January 27, 1997.
  87. 1997 MODERN MICROPROCESSOR ARCHITECTURES, Digital Equipment Corporation, Hudson, Massachusetts, January 31, 1997.
  88. 1997 MODERN MICROPROCESSOR ARCHITECTURES: Evolution of RISC into Super-Scalars, Tutorial given at the International Solid-State Circuits Conference, San Francisco, California, February 5, 1997.
  89. 1997 Algorithm for efficient implementation of fast parallel multipliers, Seminar given at Silicon Graphics Incorporated, Mountain View, California, February 19, 1997.
  90. 1997 Develpment of fast VLSI data-pahts, Compass Design Automation, San Jose, California, March 5, 1997.
  91. 1997 algorithms for generation of high-speed data-path compilers, Cascade Design Automation, Bellevue, Washington, March 13, 1997.
  92. 1997 mapping of algorithms into technology: high-speed data-path implementation, LSI Logic Corporation, Milpitas, California, April 7, 1997.
  93. 1997 Low-Power Design Techniques in VLSI Systems, Seminar at Hewlett-Packard Company Internal Workshop, Monterey, California, May 27, 1997.
  94. 1997 adiabatic techniques for achieving low-power: experimental results, Tokyo University, Tokyo, JAPAN, June 10, 1997.
  95. 1997 clocking methodology and latch design techniques for low-power processors, Hitachi Central Research Laboratories, Kokubunji, Tokyo, JAPAN, June 16, 1997.
  96. 1997 modern microprocessor architectures: Development that lead to super-scalar implementations, SONY Corporate Headquarters, Tokyo, JAPAN, June 17, 1997.
  97. 1997 Impact of multi-media computing on computer arithmetic: is there a need for STANDARDIZATION?, Panel Presentation, 13th International Symposium on Computer Arithmetic, Asilomar, California, July 8, 1997.
  98. 1997 Differential and Pass-Transistor CMOS Logic for High-Performance Systems, 21st International IEEE Conference on Microelectronics, September 15-17, 1997, Nis, Yugoslavia.
  99. 1997 AN APPLICATION OF DYNAMIC PROGRAMMING TO THE DESIGN OF A FAST ARITHMETIC LOGIC UNIT, AT&T Seminar Series, Department of Industrial Engineering, Georgia Institute of Technology, Atlanta, Georgia, October 6, 1997.
  100. 1998 COMPARATIVE STUDY OF THE ADVANCED LATCHES AND FLIP-FLOPS FOR HIGH-PERFORMANCE AND LOW-POWER VLSI SYSTEMS, Sun Microsystems Laboratories, Sunnyvale, California, February 26, 1998.
  101. 1998 ADVANCED LATCHES AND FLIP-FLOPS FOR HIGH-PERFORMANCE AND LOW-POWER VLSI SYSTEMS, Internal Symposium on Low Power Design, Micro-Computer Research Laboratories, Intel Corporation, Hillsboro, Oregon, February 10, 1998.
  102. 1998 VLSI ARITHMETIC FOR LOW-POWER VLSI SYSTEMS, Internal Symposium on Low Power Design, Micro-Computer Research Laboratories, Intel Corporation, Hillsboro, Oregon, February 10, 1998.
  103. 1998 SUPER-SCALAR PROCESSOR ARCHITECTURE, Center for Integrated Systems, Korea Advanced Institute of Science and Technology - KAIST, Taejon, KOREA, May 22, 1998.
  104. 1998 SUPER-SCALAR PROCESSOR ARCHITECTURE, Seoul National University, Seoul, KOREA May 25, 1998.
  105. 1998 ARCHITECTURAL TRADEOFFS FOR LOW POWER, The 25th Annual International Symposium on Computer Architecture - ISCA, Barcelona, SPAIN June 28, 1998.
  106. 1999 ADVANCED LATCHES AND FLIP-FLOPS FOR HIGH-PERFORMANCE AND LOW-POWER VLSI SYSTEMS, Computer Elements Workshop, Mesa Arizona, January 18, 1999.
  107. 1999 ARITHMETIC UNITS FOR DSP AND MEDIA SIGNAL PROCESSING, MEAD DSP course, Monterey, March 9, 1999.

    108. 2000 to 2004
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  108. 2000 Comparative Analysis of Master-Slave Latches and Flip-Flops for High-Performance and Low-Power Systems, IBM Austin Research Center, Austin, Texas, February 18, 2000.
  109. 2000 Advanced Logic Design, Berkeley Summer Institute, University of California, Berkeley, June 7-9, 2000.
  110. 2000 Design Techniques for LOW POWER, ST Microelectronics, Grenoble, FRANCE, July 31, 2000.
  111. 2000 clocked timing elements in high-performance and LOW-POWER systems, ST Microelectronics, La Jolla, California, November 6, 2000.
  112. 2001 VLSI ARITHMETIC, Online Symposium for Electronics Engineers (OSEE), scheduled to be aired, 5pm EST (22pm GMT), January 23, 2001.
  113. 2001 PROCESSOR DESIGN CHALLENGES, Microprocessor Design Workshop, International Solid-State Circuits Conference, San Francisco, February 8, 2001.
  114. 2001 CLOCKED TIMING ELEMENTS FOR HIGH-PERFORMANCE AND LOW POWER VLSI SYSTEMS, IBM Sponsored Computer Architecture Seminar Series, University of Texas a Austin, February 12, 2001.
  115. 2001 COMPUTATIONAL REQUIREMENTS FOR MEDIA SIGNAL PROCESSING, Electrical and Computer Engineering Department, University of Texas at Austin, February 12, 2001.
  116. 2001 Clocked Storage Elements: Master-Slave Latches and Flip-Flops for High-Performance and Low-Power Systems, Ecole Superieure d' Ingenieurs en Electrotechnique et Electronique, ESIEE, Paris, FRANCE, March 21, 2001.
  117. 2001 Clocked Storage Elements: Master-Slave Latches and Flip-Flops for High-Performance and Low-Power Systems, Barcelona, SPAIN, March 23, 2001.
  118. 2001 VLSI ARITHMETIC: ADDERS AND MULTIPLIERS, 29ème École de Printemps d'Informatique Théorique: Arithmétique des Ordinateurs, Prapoutel-Les-Sept-Laux, FRANCE, March 26, 2001.
  119. 2001 Clocked Storage Elements: Master-Slave Latches and Flip-Flops for High-Performance and Low-Power Systems, TIMA, Grenoble, FRANCE, March 28, 2001.
  120. 2001 High-speed VLSI arithmetic units: adders and multipliers, Electrical Engineering Department Colloquia, University of California Los Angeles, May 10, 2001.
  121. 2001 Timing Elements and Timing issues in High-Performance Processors, Event sponsored by CAS Distinguished Lecturer Program and by IEEE French Section, Institut Supérieur d'Electronique de Paris, Paris, FRANCE, May 29, 2001.
  122. 2001 Modern Microprocessor Architectures: Evolution of RISC into Super Scalar, Event sponsored by CAS Distinguished Lecturer Program and by IEEE French Section, Institut Supérieur d'Electronique de Paris, Paris, FRANCE, May 29, 2001.
  123. 2001 Low-Power Design Techniques in Digital Systems, IEEE Workshop on Low-Power Design, FTFC 2001: Faible Tension Faible Consommation, Paris, FRANCE, May 30 - June 1st, 2001.
  124. 2001 Will start-ups outperform big COMPANIES?, Panel Presentation, IEEE, 2001 Symposium on VLSI Circuits, Righa Royal Hotel Kyoto, Kyoto, JAPAN, June 14, 2001.
  125. 2001 Clocked Storage Elements for High-Performance Applications, Fujitsu Laboratories, Kawasaki, Tokyo, JAPAN, June 18, 2001.
  126. 2001 Clocked Storage Elements for High-Performance and Low-Power SystemS, Invited Tutorial given at the International Conference on Computer Design, ICCD 2001, Austin, Texas, September 24, 2001.
  127. 2002 DESIGN OF CLOCKED STORAGE ELEMENTS, Center for Integrated Systems, Stanford University, California, January 22, 2002.
  128. 2002 DESIGN OF CLOCKED STORAGE ELEMENTS, Dean's Seminar, College of Engineering, University of California, Santa Cruz, California, January 31, 2002.
  129. 2002 DESIGN OF SEQUENTIAL ELEMENTS, ISSCC Microprocessor Design Workshop: "High-Frequency Clocking - Issues and Solutions for Clocking High-Frequency Microprocessors", Thursday, February 7th, 2002, San Francisco.
  130. 2002 Modern Microprocessor Architectures: Evolution of RISC into Super Scalar, Invited Lecture, University of Hawaii at Manoa, Honolulu, Hawaii, March 20, 2002.
  131. 2002 Low-Power Design Techniques in Digital Systems, IEEE CAS Distinguished Lecture, IEEE Section, Honolulu, Hawaii, March 21, 2002.
  132. 2002 Clocked Storage Elements for High-Performance and Low-Power Systems, Invited Tutorial given at the IEEE Solid-State Circuits Chapter Meeting, Dallas, Texas , March 25, 2001.
  133. 2002 MODERN MICROPROCESSOR ARCHITECTURES: EVOLUTION OF RISC INTO SUPER-SCALARS, Invited Lecture, Electrical Engineering Colloquium, Department of Electrical Engineering, University of Texas at Dallas, March 26, 2002.
  134. 2002 Low-Power Design Techniques in Digital Systems, Invited Lecture, Electrical and Computer Engineering Department, University of Texas at Austin, Austin, Texas, March 27, 2002.
  135. 2002 Modern Microprocessor Architectures: Evolution of RISC into Super Scalar, Invited Lecture, Department of Electronics Computer Science and Systems, University of Calabria, Arcavacata di Rende, RENDE, ITALY, April 23, 2002.
  136. 2002 Low-Power Design Techniques in Digital Systems, Invited Lecture, Department of Electronics Computer Science and Systems, University of Calabria, Arcavacata di Rende, RENDE, ITALY, April 24, 2002.
  137. 2002 Low-Power Design Techniques in Digital Systems, Invited Lecture, ST Micorelectronics, Research and Development Division, Catania, ITALY, April 30, 2002.
  138. 2002 Modern Microprocessor Architectures: Evolution of RISC into Super Scalar, Distinguished Lecture, Electrical Engineering and Computer Sciences Department, University of Novi Sad, Novi Sad, Yugoslavia, May 9, 2002.
  139. 2002 Modern Microprocessor Architectures: Evolution of RISC into Super Scalar, Distinguished Lecture, Electrical Engineering Department, University of Belgrade, Belgrade, Yugoslavia, May 10, 2002.
  140. 2002 Low-Power Design Techniques in Digital Systems, Distinguished Lecture, Electrical Engineering Department, University of Belgrade, Belgrade, Yugoslavia, May 10, 2002.
  141. 2002 High-speed VLSI arithmetic units: adders and multipliers, Distinguished IEEE Solid-State Circuits Society Lecture, Electrical Engineering Department, University of Nis, Nis, Yugoslavia, May 13, 2001.
  142. 2002 Modern Microprocessor Architectures: Evolution of RISC into Super Scalar, Distinguished IEEE Solid-State Circuits Society Lecture, Electrical Engineering Department, University of Nis, Nis, Yugoslavia, May 13, 2001.
  143. 2002 A METHOD FOR SPEED OPTIMIZED PARTIAL PRODUCT REDUCTION AND GENERATION OF FAST PARALLEL MULTIPLIERS USING AN ALGORITHMIC APPROACH, Intel Microprocessor Research Laboratories, Hillsboro, Oregon, August 1, 2002.
  144. 2002 FUTURE DIRECTIONS IN CLOCKING MULTI-GHZ SYSTEMS, Invited Talk, International Symposium on Low-Power Electronics and Design, Monterey, California, August 12-14, 2002.
  145. 2002 Clocked Storage Elements in Multi-GHz Design, Intel Microprocessor Research Laboratories, Hillsboro, Oregon, August 23, 2002.
  146. 2002 Energy-Delay Estimation Tool and Analysis: Application on Representative VLSI Adder Topologies, Intel Microprocessor Research Laboratories, Hillsboro, Oregon, August 23, 2002.
  147. 2002 Performance Comparison of VLSI Adders Using Logical Effort, Invited Talk, 12th International Workshop on Power and Timing Modeling, Optimization and Simulation - PATMOS 2002, Seville, Spain, September 11 - 13, 2002.
  148. 2002 CLOCKING AND CLOCKED STORAGE ELEMENTS IN GHZ ENVIORMNENT, Instituto de Microelectrónica de Sevilla, E.T.S.I. Informática, Centro Nacional de Microelectrónica, Universidad de Sevilla, Sevilla, SPAIN, September 16, 2002.
  149. 2002 MODERN MICROPROCESSOR ARCHITECTURES, IEEE Distinguish Lecture, University of Patras, Patras, GREECE, December 16, 2002.
  150. 2002 MODERN MICROPROCESSOR DEVELOPMENT PERSPECTIVE, Keynote Address, 25th Anniversary of the Electrical Engineering Department, University of Banja Luka, Banja Luka, Serbian Republic, December 21, 2002.
  151. 2003 OPTIMIZING HIGH-PERFORMANCE DIGITAL CIRCUITS IN ENERGY CONSTRAINED ENVIRONMENT, Invited Presentation, 4eme journes d'etudes Faible Tension Faible Consummation, FTFC'2003, Cercle National des Armees, Paris, FRANCE, May 15, 2003.
  152. 2003 DESIGN OF POWER EFFICIENT VLSI ARITHMETIC: SPEED AND POWER TRADE-OFFS: Part-I, Part-II, Invited Tutorial, 16th IEEE Symposium on Computer Arithmetic, Santiago de Compostela, SPAIN, June 15-18, 2003.
  153. 2003 OPTIMZING HIGH-PERFORMANCE DIGITAL CIRCUITS IN ENERGY CONSTRAINED ENVIRONMENT, Instituto de Informatica, Grupo de Arquitectura de Computadores, Escuela Tecnica Superior Ingenieria, Universidad de Santiago de Compostela, Santiago de Compostela, SPAIN, June 20, 2003.
  154. 2003 CLOCKED STORAGE ELEMENTS FOR HIGH-PERFORMANCE AND LOW-POWER SYSTEMS (part-I, part-II), IEEE Distinguished Lecture, Microelectronic Systems Laboratory, Institute of Microelectronics and Microsystems, Switzerland (West) Chapter of IEEE Solid-State Circuits Society, Swiss Federal Institute of Technology, Lausanne, SWITZERLAND, June 23, 2003.
  155. 2003 DESIGN OF HIGH-PERFORMANCE ENERGY-EFFICIENT VLSI ARITHMETIC UNITS, Bart Zeydel, Invited Talk, Computer Engineering Department, Technical University of Delft, Delft, Netherlands, October 2, 2003.
  156. 2003 CLOCKED STORAGE ELEMENTS FOR HIGH-PERFORMANCE AND LOW-POWER SYSTEMS, Samsung LSI Research Laboratories, Seoul, KOREA, September 5, 2003.
  157. 2003 MICROPROCESSOR DEVELOPMENT PERSPECTIVE, IEEE Distinguished Lectures Series, Korea IEEE Solid-State Circuits Chapter, Korea University, Seoul, KOREA, September 17, 2003.
  158. 2003 CLOCKED STORAGE ELEMENTS FOR HIGH-PERFORMANCE AND LOW-POWER SYSTEMS, Center for Embedded Systems, Seoul National University, Seoul, KOREA, October 7, 2003.
  159. 2003 MICROPROCESSOR DEVELOPMENT PERSPECTIVE, IEEE Distinguished Lecture, China IEEE Solid-State Circuits Chapter, Beijing Branch, Institute of Microelectronics, Tsinghua University, Beijing, P.R. CHINA, October 20, 2003.
  160. 2003 FUTURE DIRECTIONS IN CLOCKING MULTI-GHZ SYSTEMS, Microprocessor R&D Center, Department of Computer Science, Peking University, Beijing, P.R. CHINA, October 22, 2003.
  161. 2003 BALANCING BETWEEN DESIGN AND DESIGN AUTOMATION, Invited, Panel Discussion Presentation, 5th International Conference on ASIC, Beijing, P.R. China, October 23, 2003.
  162. 2003 MULTI GHZ SYSTEM CLOCKING, Invited Presentation, 5th International Conference on ASIC, Beijing, P.R. China, October 24, 2003.
  163. 2003 POWER EFFICIENT VLSI ARITHMETIC: SPEED AND POWER TRADE-OFFS, IEEE Seoul Solid-State Circuits Chapter Distinguished Lecture, School of Electrical and Electronic Engineering, Yonsei University, Seoul, KOREA, October 31, 2003.
  164. 2003 ENERGY MINIMIZATION METHOD FOR OPTIMAL ENERGY-DELAY, Fujitsu Research Laboratories, Kawasaki, JAPAN, December 3, 2003.
  165. 2003 CLOCKED STORAGE ELEMENTS IN HIGH-PERFORMANCE AND LOW-POWER PROCESSORS, Hitachi Research Laboratories, Kokubunji, JAPAN, December 5, 2003.
  166. 2003 MICROPROCESSOR DEVELOPMENT PERSPECTIVE, IEEE Distinguished Lecture, Fudan University, Shanghai, P.R. CHINA, December 25, 2003.
  167. 2003 MICROPROCESSOR DEVELOPMENT PERSPECTIVE, Institute of VLSI Design, Zhejiang University, Hangzhou, P.R. CHINA, December 26, 2003.
  168. 2004 POWER EFFICIENT VLSI ARITHMETIC, Departamento de Technologia Electronica, Universidad de Sevilla, Sevilla, SPAIN, May 6, 2004.
  169. 2004 CLOCKING MULTI-GHZ SYSTEMS, Departamento de Technologia Electronica, Universidad de Sevilla, Sevilla, SPAIN, May 7, 2004.
  170. 2004 ENERGY-DELAY RELATIONSHIP IN DIGITAL CIRCUITS DESIGN, Invited presentation, 24th IEEE Internacional Conference on Microelectronics, Nis, SERBIA, May 18, 2004.
  171. 2004 POWER EFFICIENT DESIGN: SPEED AND POWER TRADE-OFFS, Laboratoire de l'Informatique du Parallélisme, Ecole Normale Superieure de Lyon, Lyon, FRANCE, June 17, 2004.
  172. 2004 ENERGY MINIMIZATION METHOD FOR OPTIMAL ENERGY-DELAY, "Leakage, Energy and Speed in Digital Circuits" advanced seminar organized by TIMA Laboratory, Grenoble, France, June 15, 2004.
  173. 2004 ENERGY MINIMIZATION FOR OPTIMAL ENERGY-DELAY, Infineon, Munich, GERMANY, June 23, 2004.
  174. 2004 CLOCKED STORAGE ELEMENTS FOR HIGH-PERFORMANCE AND LOW-POWER SYSTEMS, Infineon, Munich, GERMANY, June 23, 2004.
  175. 2004 DIGITAL CIRCUITS OPTIMIZATION IN ENERGY-DELAY SPACE, Intel Advanced Microprocessor Research Laboratory, Hillsboro, Oregon, December 6, 2004.

    2005 to 2010
    [back to top]

  1. 2005 CLOCKING OF DIGITAL SYSTEMS FOR HIGH-PERFORMANCE AND LOW-POWER, Tutorial Presentation, International Symposium on Circuits and Systems, Kobe, JAPAN, May 23, 2005.
  2. 2005 DESIGNING ENERGY EFFICIENT CMOS CIRCUITS, SRC Forum, June 24, 2005.
  3. 2005 ENERGY-DELAY TRADE-OFF IN CMOS DIGITAL CIRCUITS DESIGN, National Chiao Tung University, Hsinchu, Taiwan, June 30, 2005.
  4. 2005 DESIGNING ENERGY EFFICIENT CMOS CIRCUITS, School of Electrical and Computer Engineering, Royal Melbourne Institute of Technology, Melbourne, Victoria, AUSTRALIA, July 8, 2005.
  5. 2005 DESIGNING ENERGY EFFICIENT CMOS CIRCUITS, Department of Electrical and Electronic Engineering seminar, The University of Melbourne, Victoria, AUSTRALIA, July 8, 2005.
  6. 2005 ENERGY-DELAY TRADE-OFF IN CMOS DIGITAL CIRCUITS, School of Electrical and Electronic Engineering, The University of Adelaide, Adelaide, AUSTRALIA, July 26, 2005.
  7. 2005 DESIGNING ENERGY EFFICIENT CMOS CIRCUITS, Presentation at the meeting of the Swedish Foundation for Strategic Research, Linkoping, SWEDEN, August 25, 2005.
  8. 2005 LOW POWER DESIGN OF CMOS DIGITAL CIRCUITS, IEEE Solid-State Distinguished Lecture, IEEE-SSC Sweden Chapter, Linkoping University, SWEDEN, August 26, 2005.
  9. 2005 DIGITAL SYSTEM CLOCKING: HIGH-PERFORMANCE AND LOW-POWER ASPECTS, Invited Tutorial, 8th EUROMICRO Conference on Digital System Design, Porto, PORTUGAL, August 30, 2005.
  10. 2005 LOW-POWER DESIGN METHODOLOGY FOR CMOS DIGITAL CIRCUITS: APPLICATION TO STANDARD LIBRARIES, Presentation at UMC, Hsinchu, TAIWAN, September 30, 2005.
  11. 2005 ENERGY-DELAY TRADE-OFF IN CMOS DIGITAL CIRCUITS DESIGN, Presentation at Dallas IEEE CAS Workshop, Richardson, Texas, October 10, 2005.
  12. 2005 CLOCK SKEW ABSORBING FLIP-FLOP DESIGN AND DIGITAL TIMING PARTITION, Tutorial Presentation, UMC, Hsinchu, TAIWAN, October 31, 2005.
  13. 2005 ENERGY-EFFICIENT OPTIMIZATION OF THE VITERBI ACS UNIT ARCHITECTURE, Presentation at the 1st Asian Solid-State Circuits Conference, Hsinchu, TAIWAN, November 2, 2005.
  14. 2006 MICROPROCESSOR DEVELOPMENT: RETROSPECTIVE AND FUTURE CHALLENGES, Invited presentation, School of Information Technology, Sydney University, Sydney, AUSTRALIA, July 12, 2006.
  15. 2006 FUTURE OF MICROPROCESSORS: RETROSPECTIVE AND CHALLENGES, IEEE Distinguished Lecture, IEEE Western Australia Section. ICT Innovation Centre, Perth, AUSTRALIA, November 6, 2006.
  16. 2006 DIRECTIONS IN COMPUTER ENGINEERING, Keynote Presentation, The Seventh Postgraduate Electrical Engineering and Computing Symposium, PEECS 2006, Murdoch University, Perth, Western Australia, November 7, 2006.
  17. 2006 VLSI ARITHMETIC: METHODOLOGY FOR ENERGY-EFFICIENT DESIGN OF DIGITAL CIRCUITS, IEEE Distinguished Lecture, Fudan University, Shanghai, P.R. China, November 16, 2006.
  18. 2006 VLSI ARITHMETIC: METHODOLOGY FOR ENERGY-EFFICIENT DESIGN OF DIGITAL CIRCUITS, IEEE Distinguished Lecture, Tsinghua University, Beijing, P.R. China, November 18, 2006.
  19. 2007 ENERGY-DELAY TRADE-OFFS IN CMOS DIGITAL CIRCUITS DESIGN: Cadence Berkeley Research Laboratory, Berkeley, February 9, 2007.
  20. 2007 MICROPROCESSOR DEVELOPMENT: RETROSPECTIVE AND FUTURE CHALLENGES, Invited presentation, Department of Computer Science, University of Otago, Dunedin, New Zealand, April 17, 2007.
  21. 2007 LOW-POWER DESIGN TECHNIQUES IN DIGITAL SYSTEMS, IEEE and HKN Distinguished Lecture, Department of Electrical Engineering, University of Texas at San Antonio, San Antonio, Texas, November 16, 2007.
  22. 2008 LOW-POWER DESIGN TECHNIQUES IN DIGITAL SYSTEMS, Department of Electrical Engineering, University of Belgrade, Belgrade, SERBIA, May 16, 2008.
  23. 2008 DIRECTIONS IN COMPUTER ENGINEERING, Department of Electrical Engineering, University of Belgrade, Belgrade, SERBIA, May 20, 2008.
  24. 2008 LOW-POWER DESIGN AND ENERGY-DELAY RELATIONSHIP IN DIGITAL SYSTEMS, IEEE Distinguished Lecture, Department of Electrical Engineering, Bogazici University, Istanbul, TURKEY, May 29, 2008.
  25. 2008 LOW-POWER DESIGN AND ENERGY-DELAY RELATIONSHIP IN DIGITAL SYSTEMS, IEEE Distinguished Lecture, Department of Electrical Engineering, Istanbul Technical University, Istanbul, TURKEY, May 29, 2008.
  26. 2008 MICROPROCESSOR DEVELOPMENT: RETROSPECTIVE AND FUTURE CHALLENGES, Keynote Speaker, IEEE International Conference on Microelectronics, ICM 2008, Sharjah University, Sharjah, United Arab Emirates, December 15, 2008.
  27. 2008 LOW-POWER DESIGN TECHNIQUES, Invited Speaker, Engineering Department, University of Sharjah, United Arab Emirates, December 16, 2008.
  28. 2009 LOW-POWER DESIGN OF CMOS DIGITAL CIRCUITS, Taiwan Semiconductor Manufacturing Corp. - TSMC, Hsinchu, TAIWAN, May 26, 2006.
  29. 2009 LOW-POWER DESIGN TECHNIQUES IN DIGITAL SYSTEMS, Invited Tutorial, IEEE Midwest Symposium on Circits and Systems, Cancun, MEXICO, August 2, 2009.
  30. 2009 METHODOLOGY FOR ENERGY-EFFICIENT DESIGN OF DIGITAL CIRCUITS, Invited Lecture, Computer Engineering Colloquium, TU Delft - Delft University of Technology, Delft, THE NETHERLANDS, September 9, 2009.
  31. 2009 A NEW METHODOLOGY FOR POWER-AWARE TRANSISTOR SIZING: FREE POWER RECOVERY (FPR), PATMOS 2009, Delft, THE NETHERLANDS, September 11, 2009.
  32. 2009 COMPUTING AT THE ULTIMATE LOW-ENERGY LIMITS, Invited Lecture, CMOS Emerging Technologies Workshop, CANADA, September 25, 2009.
  33. 2009 METHODOLOGY FOR ENERGY-EFFICIENT DESIGN OF DIGITAL CIRCUITS, IEEE Distinguished Lecture, IEEE Solid-State Circuits Society, Germany Chapter, Hanover University, Hanover, GERMANY, October 7, 2009.
  34. 2009 METHODOLOGY FOR ENERGY-EFFICIENT DESIGN OF DIGITAL CIRCUITS, IEEE Distinguished Lecture, IEEE Solid-State Circuits Society, Ireland Chapter, Tyndall National Institute and the University of Cork, IRELAND, October 9, 2009.
  35. 2009 METHODOLOGY FOR ENERGY-EFFICIENT DESIGN OF DIGITAL CIRCUITS, Invited Speaker, The Hong-Kong University of Science and Technology, Hong-Kong, October 19, 2009.
  36. 2010 METHODOLOGY FOR ENERGY-EFFICIENT DESIGN OF DIGITAL CIRCUITS, IEEE Distinguished Lecture, IEEE Solid-State Circuits Society, Santa Clara Valley Chapter, April, 15, 2010.
  37. 2010 METHODOLOGY FOR ENERGY-EFFICIENT DESIGN OF DIGITAL CIRCUITS, Southern Methodist University, Computer Science and Engineering Seminar, Dallas, Texas, April, 22, 2010.
  38. 2010 LOW-POWER DESIGN, Euro Program Short Course, Engineering Department, University of Bologna, Bologna, ITALY, May, 24-27, 2010.
  39. 2010 METHODOLOGY FOR ENERGY-EFFICIENT DESIGN OF DIGITAL CIRCUITS, Advanced Micro Devices, Austin, Texas, August, 20, 2010.
  40. 2010 ENERGY-EFFICIENT DESIGN OF DIGITAL CIRCUITS, Invited Tutorial, 23th Symposium on Integrated Circuits and System Design, Bourbon Convention Center, Ibirapuera, Sao Paolo, BRAZIL, September 6, 2010.
  41. 2010 COMPUTING AT THE ULTIMATE LOW-ENERGY LIMITS, Invited paper, 23th Symposium on Integrated Circuits and System Design, Bourbon Convention Center, Ibirapuera, Sao Paolo, BRAZIL, September 6, 2010.

    42. 2010 - on
    [back to top]

  42. 2011 METHODOLOGY FOR ENERGY-EFFICIENT DESIGN OF DIGITAL CIRCUITS, IEEE Distinguished Lecture, IEEE Solid-State Circuits & IEEE CAS Chapter, Porto Alegre, BRAZIL, May 20, 2011.
  43. 2011 A QUICK METHOD FOR ENERGY OPTIMIZED GATE SIZING OF DIGITAL CIRCUITS, 21st International Workshop, PATMOS 2011 on Power and Timing Modeling, Optimization, and Simulation, Madrid, SPAIN, September 27, 2011.
  44. 2011 MICROPROCESSOR DEVELOPMENT: RETROSPECTIVE AND FUTURE CHALLENGES, Seminar, Universidad Pontifica Comillas, Madrid, SPAIN, September 30, 2011.
  45. 2012 METHODOLOGY FOR ENERGY-EFFICIENT DESIGN OF DIGITAL CIRCUITS, Invited Presentation, Conferencia Argentina de Micro-Nanoelectrónica, Tecnologías y sus Aplicaciones – CAMTA, Cordoba, Argentina, Augusto 9, 2012.
  46. 2012 LOW-POWER DESIGN IN 5 EASY STEPS, Short Course given at: Conferencia Argentina de Micro-Nanoelectrónica, Tecnologías y sus Aplicaciones – CAMTA, Cordoba, Argentina, Augusto 9, 2012.
  47. 2012 IEEE CIRCUITS AND SYSTEMS: NEW PERSPECTIVES AND VISION, Simposio Argentino de Sistemas Embebidos, SASE 2012, Facultad de Ingenieria - Universidad de Buenos Aires, Buenos Aires, Argentina, August 15, 2012.
  48. 2015 MINIMIZING ENERGY BY ACHIEVING OPTIMAL SPARSENESS IN PARALLEL ADDERS, 22nd IEEE Symposium on Computer Arithmetic, Lyon, FRANCE, June 22-24, 2015.
 
 
 
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