The critical path of an adder is the longest path a carry needs to propagate through. In previously published 64-bit adders, the one with shortest critical path has six stages. In the proposed research, we intend to identify features of existing carry propagation schemes that are advantageous toward higher speed and lower energy. First, a review of state-of-the-art designs is given in energy-delay space, then the design parameters are evaluated and their performances are estimated under assumed environment. Finally, a high-performance and energy-efficient adder will be designed and fabricated using sub-100nm CMOS technology.