The following script is the TCL version of the synthesis script. It sources the TCL setup file. It assumes the tech library is setup for the "typical" operating conditions, and forces the synthesis tool to only use simple D-type flip-flops.
#
#/*******************************************/
#/* Script to compile leon with synopsys DC */
#/* Gabriel Ricardo, UCDavis ACSEL, 2003 */
#/*******************************************/
#/* paths to target and link libraries set in .synopsys_dc.setup file in working dir. */
source .synopsys_dctcl.setup
#/* Force library to only use plain D-type flip-flops */
set_dont_use typical_detff/DFFRX1
set_dont_use typical_detff/DFFRX2
set_dont_use typical_detff/DFFRX4
set_dont_use typical_detff/DFFRXL
set_dont_use typical_detff/DFFNSX1
set_dont_use typical_detff/DFFNSX2
set_dont_use typical_detff/DFFNSX4
set_dont_use typical_detff/DFFNSXL
set_dont_use typical_detff/DFFNRX1
set_dont_use typical_detff/DFFNRX2
set_dont_use typical_detff/DFFNRX4
set_dont_use typical_detff/DFFNRXL
set_dont_use typical_detff/DFFNSRX1
set_dont_use typical_detff/DFFNSRX2
set_dont_use typical_detff/DFFNSRX4
set_dont_use typical_detff/DFFNSRXL
set_dont_use typical_detff/DFFRHQX1
set_dont_use typical_detff/DFFRHQX2
set_dont_use typical_detff/DFFRHQX4
set_dont_use typical_detff/DFFRHQXL
set_dont_use typical_detff/DFFSX1
set_dont_use typical_detff/DFFSX2
set_dont_use typical_detff/DFFSX4
set_dont_use typical_detff/DFFSXL
set_dont_use typical_detff/DFFSHQX1
set_dont_use typical_detff/DFFSHQX2
set_dont_use typical_detff/DFFSHQX4
set_dont_use typical_detff/DFFSHQXL
####set_dont_use typical_detff/DFFSRX1
set_dont_use typical_detff/DFFSRX2
set_dont_use typical_detff/DFFSRX4
set_dont_use typical_detff/DFFSRXL
set_dont_use typical_detff/DFFSRHQX1
set_dont_use typical_detff/DFFSRHQX2
set_dont_use typical_detff/DFFSRHQX4
set_dont_use typical_detff/DFFSRHQXL
set_dont_use typical_detff/DFFTRX1
set_dont_use typical_detff/DFFTRX2
set_dont_use typical_detff/DFFTRX4
set_dont_use typical_detff/DFFTRXL
set_dont_use typical_detff/JKFFX1
set_dont_use typical_detff/JKFFX2
set_dont_use typical_detff/JKFFX4
set_dont_use typical_detff/JKFFXL
set_dont_use typical_detff/JKFFRX1
set_dont_use typical_detff/JKFFRX2
set_dont_use typical_detff/JKFFRX4
set_dont_use typical_detff/JKFFRXL
set_dont_use typical_detff/JKFFSRX1
set_dont_use typical_detff/JKFFSRX2
set_dont_use typical_detff/JKFFSRX4
set_dont_use typical_detff/JKFFSRXL
set_dont_use typical_detff/JKFFSX1
set_dont_use typical_detff/JKFFSX2
set_dont_use typical_detff/JKFFSX4
set_dont_use typical_detff/JKFFSXL
set_dont_use typical_detff/SDFFX1
set_dont_use typical_detff/SDFFX2
set_dont_use typical_detff/SDFFX4
set_dont_use typical_detff/SDFFXL
set_dont_use typical_detff/SDFFHQX1
set_dont_use typical_detff/SDFFHQX2
set_dont_use typical_detff/SDFFHQX4
set_dont_use typical_detff/SDFFHQXL
set_dont_use typical_detff/SDFFRX1
set_dont_use typical_detff/SDFFRX2
set_dont_use typical_detff/SDFFRX4
set_dont_use typical_detff/SDFFRXL
set_dont_use typical_detff/SDFFRHQX1
set_dont_use typical_detff/SDFFRHQX2
set_dont_use typical_detff/SDFFRHQX4
set_dont_use typical_detff/SDFFRHQXL
set_dont_use typical_detff/SDFFSX1
set_dont_use typical_detff/SDFFSX2
set_dont_use typical_detff/SDFFSX4
set_dont_use typical_detff/SDFFSXL
set_dont_use typical_detff/SDFFSHQX1
set_dont_use typical_detff/SDFFSHQX2
set_dont_use typical_detff/SDFFSHQX4
set_dont_use typical_detff/SDFFSHQXL
set_dont_use typical_detff/SDFFSRX1
set_dont_use typical_detff/SDFFSRX2
set_dont_use typical_detff/SDFFSRX4
set_dont_use typical_detff/SDFFSRXL
set_dont_use typical_detff/SDFFSRHQX1
set_dont_use typical_detff/SDFFSRHQX2
set_dont_use typical_detff/SDFFSRHQX4
set_dont_use typical_detff/SDFFSRHQXL
set_dont_use typical_detff/SDFFTRX1
set_dont_use typical_detff/SDFFTRX2
set_dont_use typical_detff/SDFFTRX4
set_dont_use typical_detff/SDFFTRXL
set_dont_use typical_detff/SEDFFX1
set_dont_use typical_detff/SEDFFX2
set_dont_use typical_detff/SEDFFX4
set_dont_use typical_detff/SEDFFXL
set_dont_use typical_detff/SEDFFHQX1
set_dont_use typical_detff/SEDFFHQX2
set_dont_use typical_detff/SEDFFHQX4
set_dont_use typical_detff/SEDFFHQXL
set_dont_use typical_detff/SEDFFTRX1
set_dont_use typical_detff/SEDFFTRX2
set_dont_use typical_detff/SEDFFTRX4
set_dont_use typical_detff/SEDFFTRXL
set_dont_use typical_detff/EDFFX1
set_dont_use typical_detff/EDFFX2
set_dont_use typical_detff/EDFFX4
set_dont_use typical_detff/EDFFXL
set_dont_use typical_detff/EDFFTRX1
set_dont_use typical_detff/EDFFTRX2
set_dont_use typical_detff/EDFFTRX4
set_dont_use typical_detff/EDFFTRXL
#/* Define system timing parameters */
set frequency 200
set clock_skew 0.10
set input_setup 2.0
set output_delay 2.0
#/* don't touch anything from here unless you know what you are doing */
set hdlin_ff_always_sync_set_reset true
set hdlin_translate_off_skip_text true
sh rm -rf WORK
sh mkdir WORK
define_design_lib WORK -path WORK
analyze -f VHDL -library WORK ../leon/amba.vhd
analyze -f VHDL -library WORK ../leon/target.vhd
analyze -f VHDL -library WORK ../leon/device.vhd
analyze -f VHDL -library WORK ../leon/config.vhd
analyze -f VHDL -library WORK ../leon/sparcv8.vhd
analyze -f VHDL -library WORK ../leon/iface.vhd
analyze -f VHDL -library WORK ../leon/macro.vhd
analyze -f VHDL -library WORK ../leon/bprom.vhd
analyze -f VHDL -library WORK ../leon/multlib.vhd
analyze -f VHDL -library WORK ../leon/tech_generic.vhd
analyze -f VHDL -library WORK ../leon/tech_virtex.vhd
analyze -f VHDL -library WORK ../leon/tech_atc25.vhd
analyze -f VHDL -library WORK ../leon/tech_atc35.vhd
analyze -f VHDL -library WORK ../leon/tech_fs90.vhd
analyze -f VHDL -library WORK ../leon/tech_tsmc25.vhd
analyze -f VHDL -library WORK ../leon/tech_tsmc18.vhd
analyze -f VHDL -library WORK ../leon/tech_umc18.vhd
analyze -f VHDL -library WORK ../leon/tech_proasic.vhd
analyze -f VHDL -library WORK ../leon/tech_axcel.vhd
analyze -f VHDL -library WORK ../leon/tech_map.vhd
analyze -f VHDL -library WORK ../leon/cachemem.vhd
analyze -f VHDL -library WORK ../leon/icache.vhd
analyze -f VHDL -library WORK ../leon/dcache.vhd
analyze -f VHDL -library WORK ../leon/acache.vhd
analyze -f VHDL -library WORK ../leon/cache.vhd
analyze -f VHDL -library WORK ../leon/ambacomp.vhd
analyze -f VHDL -library WORK ../leon/apbmst.vhd
analyze -f VHDL -library WORK ../leon/ahbmst.vhd
analyze -f VHDL -library WORK ../leon/ahbstat.vhd
analyze -f VHDL -library WORK ../leon/ahbtest.vhd
analyze -f VHDL -library WORK ../leon/ahbarb.vhd
analyze -f VHDL -library WORK ../leon/lconf.vhd
analyze -f VHDL -library WORK ../leon/fpulib.vhd
analyze -f VHDL -library WORK ../leon/fpu_lth.vhd
analyze -f VHDL -library WORK ../leon/meiko.vhd
analyze -f VHDL -library WORK ../leon/fpu_core.vhd
analyze -f VHDL -library WORK ../leon/ioport.vhd
analyze -f VHDL -library WORK ../leon/irqctrl.vhd
analyze -f VHDL -library WORK ../leon/sdmctrl.vhd
analyze -f VHDL -library WORK ../leon/mctrl.vhd
analyze -f VHDL -library WORK ../leon/rstgen.vhd
analyze -f VHDL -library WORK ../leon/timers.vhd
analyze -f VHDL -library WORK ../leon/uart.vhd
analyze -f VHDL -library WORK ../leon/mul.vhd
analyze -f VHDL -library WORK ../leon/div.vhd
analyze -f VHDL -library WORK ../leon/iu.vhd
analyze -f VHDL -library WORK ../leon/dcom_uart.vhd
analyze -f VHDL -library WORK ../leon/dcom.vhd
analyze -f VHDL -library WORK ../leon/dsu_mem.vhd
analyze -f VHDL -library WORK ../leon/dsu.vhd
analyze -f VHDL -library WORK ../leon/proc.vhd
analyze -f VHDL -library WORK ../leon/wprot.vhd
analyze -f VHDL -library WORK ../leon/mcore.vhd
analyze -f VHDL -library WORK ../leon/leon.vhd
elaborate leon
current_design leon
uniquify
ungroup [find cell "*pad*"] -flatten
current_instance mcore0
group [find cell [list "wp*" "asm*" "apb*" "uart*" "timer*" "irq*" "iopo*" "ahb*" "*mctrl*" "
lc*" "reset*" "dcom*"]] -design_name amod -cell_name amod0
current_instance amod0
ungroup -all -flatten -simple_names
current_instance ../proc0/iu0
ungroup -all -flatten -simple_names
current_instance ../rf0
ungroup -all -flatten -simple_names
current_instance ../c0
ungroup -all -flatten -simple_names
current_instance ../cmem0
ungroup -all -flatten -simple_names
current_instance ../../..
ungroup clkgen0 -flatten -simple_names
set peri [expr 1000.0 / $frequency]
set input_delay [expr $peri - $input_setup]
set tdelay [expr $output_delay + 2]
create_clock -name "clk" -period $peri -waveform [list 0.0 [expr $peri / 2.0]] [list "clk"]
set_wire_load_mode segmented
set_clock_uncertainty -hold $clock_skew "clk"
set_clock_uncertainty -setup $clock_skew "clk"
set_input_delay $input_delay -clock clk [list {pio[15]} {pio[14]} {pio[13]} {pio[12]} {pio[11
]} {pio[10]} {pio[9]} {pio[8]} {pio[7]} {pio[6]} {pio[5]} {pio[4]} {pio[3]} {pio[2]} {pio[1]}
{pio[0]} {data[31]} {data[30]} {data[29]} {data[28]} {data[27]} {data[26]} {data[25]} {data[
24]} {data[23]} {data[22]} {data[21]} {data[20]} {data[19]} {data[18]} {data[17]} {data[16]}
{data[15]} {data[14]} {data[13]} {data[12]} {data[11]} {data[10]} {data[9]} {data[8]} {data[7
]} {data[6]} {data[5]} {data[4]} {data[3]} {data[2]} {data[1]} {data[0]} "brdyn" "bexcn"]
set_max_delay $tdelay -to [list "errorn" "wdogn" {pio[15]} {pio[14]} {pio[13]} {pio[12]} {pio
[11]} {pio[10]} {pio[9]} {pio[8]} {pio[7]} {pio[6]} {pio[5]} {pio[4]} {pio[3]} {pio[2]} {pio[
1]} {pio[0]} {data[31]} {data[30]} {data[29]} {data[28]} {data[27]} {data[26]} {data[25]} {da
ta[24]} {data[23]} {data[22]} {data[21]} {data[20]} {data[19]} {data[18]} {data[17]} {data[16
]} {data[15]} {data[14]} {data[13]} {data[12]} {data[11]} {data[10]} {data[9]} {data[8]} {dat
a[7]} {data[6]} {data[5]} {data[4]} {data[3]} {data[2]} {data[1]} {data[0]}]
set_max_delay $output_delay -to [list "writen" {romsn[1]} {romsn[0]} "read" "oen" "iosn" {rwe
n[3]} {rwen[2]} {rwen[1]} {rwen[0]} {ramsn[3]} {ramsn[2]} {ramsn[1]} {ramsn[0]} {ramoen[3]} {
ramoen[2]} {ramoen[1]} {ramoen[0]} {sdcsn[1]} {sdcsn[0]} "sdwen" "sdrasn" "sdcasn" {sddqm[3]}
{sddqm[2]} {sddqm[1]} {sddqm[0]} {address[27]} {address[26]} {address[25]} {address[24]} {ad
dress[23]} {address[22]} {address[21]} {address[20]} {address[19]} {address[18]} {address[17]
} {address[16]} {address[15]} {address[14]} {address[13]} {address[12]} {address[11]} {addres
s[10]} {address[9]} {address[8]} {address[7]} {address[6]} {address[5]} {address[4]} {address
[3]} {address[2]} {address[1]} {address[0]}]
set_max_area 0
set_max_transition 2.0 leon
set_flatten false -design [list "leon.db:leon"]
set_structure true -design [list "leon.db:leon"] -boolean false -timing true
link
compile -map_effort medium -boundary_optimization
write -f db -hier leon -output leon_zero.db
write -f verilog -hier leon -output leon_zero.v
redirect leon_zero.rpt { report_timing -nworst 1 }
current_design mcore
redirect -append leon_zero.rpt { report_area }
redirect -append leon_zero.rpt { check_design }
current_design leon
redirect leon_cells { rpt_cells -all_cells }
exit