![Home](_derived/home_cmp_glacier110_vbtn.gif)
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Systematically derived ET FF
[12]
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![](our_de12.gif)
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Transmission-Gate Flip-Flop
[15]
![bullet](_themes/glacier/aglabul2.gif) |
Two transmission gates define transparency window
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![bullet](_themes/glacier/aglabul2.gif) |
Time window with non precharge-evaluate structure
![bullet](_themes/glacier/aglabul3.gif) |
Low-input activity => low output activity
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![](TGFF.h1.gif)
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Regenerative clock pulse flip-flop with push-pull NAND latch
(RCPPN)
[18]
![bullet](_themes/glacier/aglabul2.gif) |
Triggered by regenerative pulse at Cs after Clk
falls
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![bullet](_themes/glacier/aglabul2.gif) |
Outputs Q and Qb simultaneously pulled to opposite logic
levels in critical path
![](clocke13.gif)
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![bullet](_themes/glacier/aglabul1.gif) |
Differential Regenerative clock pulse flip-flop with
push-pull latch (RCPP-D)
[18]
![bullet](_themes/glacier/aglabul2.gif) |
Triggered by regenerative pulse at Cs after Clk
falls
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![bullet](_themes/glacier/aglabul2.gif) |
Flip-flop transparent in a window defined by internal
flip-flop delays
![bullet](_themes/glacier/aglabul3.gif) |
clock uncertainty absorption
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![bullet](_themes/glacier/aglabul2.gif) |
Push-pull latch simultaneously drives Q and Qb opposite
logic levels
![](clocke15.gif)
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Conditional precharge flip-flop (CPFF)
[10]
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![bullet](_themes/glacier/aglabul1.gif) |
Conditional precharge flip-flop (DE-CPFF)
[16]
![bullet](_themes/glacier/aglabul2.gif) |
Generate transparency window to capture D after each clock
edge
![bullet](_themes/glacier/aglabul3.gif) |
No delay penalty for dual-edge clocking
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![bullet](_themes/glacier/aglabul2.gif) |
Conditional precharge - pulse generator precharges only
when needed
![](clocke20.gif)
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![bullet](_themes/glacier/aglabul1.gif) |
Symmetric pulse generator flip-flop (SPGFF)
[17]
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