Modified SAFF [20]
	Sense Amplifier based Flip-Flop (SAbFF) [20] Differential flip-flop Top stage amplifies difference between inputs Bottom stage Push-pull symmetric set-reset latch Equal low-to-high and high-to-low delays Fast - critical path like in dynamic gates Internal switching in each cycle - high power consumption

Systematically derived ET FF [12]

Transmission-Gate Flip-Flop [15] Two transmission gates define transparency window Time window with non precharge-evaluate structure Low-input activity => low output activity

 

Regenerative clock pulse flip-flop with push-pull NAND latch (RCPPN) [18] Triggered by regenerative pulse at Cs after Clk falls Outputs Q and Qb simultaneously pulled to opposite logic levels in critical path

 

Differential Regenerative clock pulse flip-flop with push-pull latch (RCPP-D) [18] Triggered by regenerative pulse at Cs after Clk falls Flip-flop transparent in a window defined by internal flip-flop delays clock uncertainty absorption Push-pull latch simultaneously drives Q and Qb opposite logic levels

Conditional precharge flip-flop (CPFF) [10] Pulse generator evaluates when Clk = CK3 = 1 (transparency window) Precharge only when D = 0 Activity of pulse generator equal to activity of input D Statistical power reduction Introduces new critical path, limiting speed

	Conditional precharge flip-flop (DE-CPFF) [16] Generate transparency window to capture D after each clock edge No delay penalty for dual-edge clocking Conditional precharge - pulse generator precharges only when needed
	Symmetric pulse generator flip-flop (SPGFF) [17] Two pulse generators active at opposite clock edges Pulse width = clock width Second stage is simple static NAND gate Strongly driven output available after two stages Latch not needed Low clock load