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PowerThe main motivation for using DET-CSEs in the implementation is to reduce the power consumption in the clock tree, which is typically by far the largest contributor to switching power in a design. To demonstrate the degree of power savings and the advantage of the DET-CSE implementation, we must analyze the power characteristics of the two implementations (with SET-CSEs and with DET-CSEs) and compare the results. PerformanceWe also have to take into consideration the impact of insertion of the DETFFs
on performance. Since data is captured on both edges of the clock, there
are separate setup times, hold times, and delays for each clock edge. This
raises issues in meeting critical path timing, race path, and clock uncertainty
on the different edges.
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