Digital
• Daytime Paper Sessions
• Evening Panel Discussions
• Tutorial
• Trend Charts
1997 ISSCC – DIGITAL
SESSION HIGHLIGHTS
- High-Performance Microprocessors
- Clocking, Phase/Delay-Locked Loops, Input/Output Drivers
- Processors, Integrated Multimedia Functions, and Logic Elements
PANEL DISCUSSION
- The Future of the Net Computer and its Impact on Microprocessors
- Synchronous vs. Asynchronous Design
TUTORIAL
- Microprocessor Architecture: RISC Evolution into Super-Scalars
Session FA10
HIGH-PERFORMANCE MICROPROCESSORS
DRIVERS
- Higher clock rate for increased performance
- Lower voltage and reduced power consumption
- Multimedia extensions built into core single-chip processors
HIGHLIGHTS
- 600MHz DEC Alpha microprocessor estimated at 40 SpecInt95 and 60
SpecFP95 [10.7]
- 533MHz BiCMOS PowerPC Microprocessor based on ECL logic [10.1]
- Intel 300MHz x86 microprocessor with 12.4 SpecInt95 and MMX
graphic-instruction-set extensions [10.4]
- AMD x86 microprocessor with MMX graphic-instruction-set extensions
[10.5]
- DEC 550MHz microprocessor with Alpha graphic-instruction-set extensions
[10.6]
- Single-chip mainframe: 350MHz IBM S/390 with redundant datapath execution
units for self-checking [10.3]
- SUN 330MHz UltraSparc II Microprocessor with flip-chip mounting for
increased interconnect pin-count [10.2]
Session SA20
CLOCKING, PLL, AND I/O CIRCUITS
DRIVERS
- Need clean low-jitter symmetric on-chip clocks
- Increased bandwidth for off-chip interconnect
HIGHLIGHTS
- 440MHz clock outputs with measured jitter <85ps [20.1]
- Self-biasing techniques to achieve huge frequency range from 0.08MHz to
400MHz [20.2]
- Dual-loop PLL to attain instantaneous frequency shifting without glitching
[20.4]
OTHER SIGNIFICANT RESULTS
- PLL with digitally-controlled oscillator [20.3]
- First practical demonstration of power-savings using off-chip inductors
for energy recovery with reduction of power from 3 to 7 times [20.5]
- Low-swing 0.2V to 0.5V I/O drivers designed to ease communication between
chips with supply voltages from <1V to 5V [20.6]
- Partial-response driver/receiver pairs to reduce I/O power by up to 90%
using RC-loaded lines at up to 500Mb/s [20.7]
Session SP25
PROCESSORS AND LOGIC ELEMENTS
DRIVERS
- Laptop computers requiring aggressive power-management
- More integration and smaller die-sizes to lower cost
HIGHLIGHTS
- Motorola 5W processor with clocking throttled by on-chip temperature
sensing [25.2]
- First HP processor with big (128kByte) on-chip caches [25.1]
- Tiny 1.27mm2 full 54x54b multiplier array at 2.5V [25.4]
OTHER SIGNIFICANT RESULTS
- Unifying review of timing choices for Domino circuits to tolerate more
skew and time-borrowing [25.3]
- An ALU using early-completion-detection to increase average throughput for
a 1GHz 64b datapath [25.5]
MOST-SIGNIFICANT RESULTS
- Relentless performance increases in all four major processor architectures
(Alpha, x86, PowerPC, Sparc) [10.7, 10.4, 10.1, 10.2]
- Increasing use of printed-circuit board and system techniques for on-chip
power-plane distribution [10.7]
- Increasing use of low-swing and communications-systems techniques for
reducing input/output link power [20.6, 20.7]
- Continued refinement of design techniques for squeezing performance.
[25.3, 25.5, 20.1]
Panel Session FE6
SYNCHRONOUS VS. ASYNCHRONOUS DESIGN
APPLICATIONS
- Efficient system sesign
- Reliable system operation
CHALLENGES
- Management of power dissipation
- Management of clock distribution
- Maintenance of robustness
- Maintain or increase in design productivity
CONTROVERSIES :
- Are asynchronous designs as cost-effective as synchronous designs?
- Can the testability problem be solved?
- Is the choice between design styles application-dependent?
- Are design-and-test tools available ?
Panel Session FE7
THE FUTURE OF THE NET COMPUTER AND ITS IMPACT ON
MICROPROCESSORS
APPLICATIONS
- Vision of a ubiquitous, mass-market appliance.
CHALLENGES
- Building an inexpensive enough consumer product.
- Standardization of both hardware and software browsers and operating
systems.
CONTROVERSIES
- Will other companies successfully compete against the Intel/Microsoft
domination?
- Will Java become a standard or a flop?
- Will consumers care about the "operating system" or can it be completely
hidden from users?
- Will the "Internet" be transmitted to homes by telephone wires, coax
cable, or wireless RF?Tutorial T3
Tutorial T3
MICROPROCESSOR ARCHITECTURE:
RISC EVOLUTION INTO
SUPER-SCALARS
Vojin Oklobdzija
OVERVIEW
- Review and comparison of microprocessor design issues
- Evolution and modern meaning of "RISC techniques"
- Contrasting super-scalar, vector, and Very-Long-Instruction-Word (VLIW)
approaches.
TUTORIAL SPEAKER BIOGRAPHY
Vojin Oklobdzija received his PhD from UCLA in 1982 and spent 8 years
as a research staff member at the IBM T.J. Watson Research Center in New York,
contributing to RISC architectures. From 1988-90 he taught at the University of
California, Berkeley. He is now a consultant with Integration Inc., in Berkeley,
California, and a Professor of Electrical and Computer Engineering at the
University of California, Davis. Professor Oklobdzija is a Fellow of the IEEE.
Microprocessor Trend: Transistor Count
Microprocessor Trend: Clock Frequency
Microprocessor Trend: ISPEC Performance
Microprocessor Trend: ISPEC/MHz
Microprocessor Trend: ISPEC/Watt
Microprocessor Trend: ISPEC2/Watt
Go back to the SSCC page
Go back to the ISSCC page
If you have any comments for the ISSCC, please forward them to
Franky Hewlett
hewletfw@sandia.gov
(505) 844-1997
(505) 844-8480 FAX
Comments related to maintenance of this web should be sent to eenguyen@ee.ust.hk.
http://eesu30.ee.ust.hk/local/isscc/1997/press/digital.htm
Last modified :
Monday November 18, 1996 at 1:26am HKT