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December 01, 1997,
New design approach recycles electrons to save power -- Clock-powered circuits set efficiency record
Monterey, Calif. - With advanced systems now burning in excess of 100 W, the search for more power-stingy approaches to system-level-silicon design has begun in earnest. One option that many researchers believe could slash power consumption is adiabatic circuit design.
At the recent International Symposium on Low-Power Electronics and Design here, one group reported on an adiabatic logic-design method that it says not only simplifies design but also increases the potential power savings by up to a factor of 10 over previous heat-conservation approaches.
The product of a team effort between Vojin Oklobdzija at the University of California-Davis and Dragan Maksimovic at the University of Colorado, Boulder, the approach has yielded two new adiabatic logic families-pass-transistor adiabatic logic (PAL) and clocked adiabatic Logic (CAL)-that differ from previous methods in that they integrate the power clock on-chip.
Meanwhile, a contrasting approach at the Massachusetts Institute of Technology's Artificial Intelligence Laboratory is realizing dense adiabatic circuits using a radically new computational paradigm based on reversible logic.
Though adiabatic circuits can be run off current CMOS fab lines, the design philosophy differs radically from that for conventional logic. Instead of supplying a constant voltage to a chip and then clocking signals through, adiabatic circuits have a periodic, sinusoidal power system that activates logic gates. Logic is evaluated on the upswing of the power curve, and energy returns to the power supply as it ramps back down. The electrical energy is thus recycled, thereby saving power.
The novel approach is being refined at several research institutions, including IBM, Bell Laboratories and Princeton University in addition to MIT and the Universities of California and Colorado.
One barrier to simple and practical adiabatic circuits has been the requirement for a high-quality sine-wave power signal. That requires inductors, which are difficult to integrate on chip. The need to condition the power signal as it moves through circuit blocks complicates matters. Past designs have had to use complicated multiple clock schemes to solve the problem, and those schemes have had implications for design.
"We tried an idea with several unsuccessful attempts at IBM and Bell Labs before finding a workable solution," Oklobdzija recalled. With PAL and CAL, "we believe that we have brought [adiabatic circuit design] a step further to something that is more realizable."
The PAL design, he said, comes in at two to four times the energy efficiency of previous approaches; the CAL family improves on those earlier approaches by a factor of 10.
The two researchers were able to get a fairly complex circuit-a 1,600-stage shift register-up and running. The circuit was fabricated in a 1.2-micron CMOS process and ran at 160 MHz with a 1.5-V peak-to-peak sinusoidal clock.
"With the logic and power clock-a recycling power generator-integrated onto a single chip, we can plug in a 1.5-V battery and simply measure the power at the terminals of the battery," said Oklobdzija.
By contrast, he said, the complicated clocking schemes of past approaches had made it difficult even to evaluate the potential power savings. For example, the Bell Labs effort used a complex external four-phase clock that made it difficult to determine on-chip power consumption.
"Our measurement is much simpler, and we are able to maintain accurate measurements of power that were not possible before," Oklobdzija said.
The technology is based on a dual-rail logic and is said to have a relatively low gate complexity; a gate typically consists of true and complementary NMOS functional blocks and a pair of cross-coupled PMOS devices.
More important, the gate structure and the single power-clock signal support a design style that is similar to current design methods. That could allow CMOS designers to build larger, more complex circuits using a design method that resembles current practice.
Theoretically, any existing logic type could be realized in the PAL and CAL families.
MIT's Artificial Intelligence Laboratory, meanwhile, has brought a processor called the Pendulum to the fabrication stage. The single-chip processor is not based on conventional random logic but instead uses a highly simplified approach to computation based on cellular automata-arrays of identical, highly simplified processing units. Each processing unit, or cell, in the array polls its nearest neighbors and updates its own internal state accordingly.
The architecture is being implemented with conventional logic and DRAM by another MIT group, which has developed a supercomputer called the Cellular Automata Machine. Rather than compute mathematical algorithms, the CAM directly simulates physical systems at the molecular or atomic level.
The MIT approach realizes a complete microprocessor, but the range of applications can be narrowed according to the specific architecture. In principle, cellular automata should be able to emulate any computing approach; but how best to do that, in terms of computational efficiency, remains a matter for research.
The MIT group is viewing reversible logic as a long-term solution to the circuit-power and circuit-density crunch. Its premise is based on the physical fact that a computation that throws away information also wastes energy.
In a reversible logic gate, the number of outputs is equal to the number of inputs, and the gate can be run backward to reproduce the inputs' preprocessed state. That capability is directly used in MIT's Charge Recovery Logic scheme to conserve electronic charge.
Studies of long-term circuit-density trends show that reversible logic asymptotically moves toward near zero power dissipation per operation, while CMOS quickly hits a wall.
For Oklobdzija at UC-Davis, a more conventional logic design approach could have some important near-term applications. "As computers become consumer appliances, it is important that they can operate as portable and battery-operated devices," he observed. "We want to integrate even more functions into smaller areas of the chip, so these techniques have to be developed."
One area in which ultra-low power circuits have a critical advantage is in satellite and space probe systems. "For example, if you sent a probe to Mars, the system would require a computer that operates from batteries and you would have to operate it for a very long time because you can't be there to change the batteries," he said.
Circuits optimized to consume an order of magnitude less power would have a critical advantage over conventional logic in such an application.
Oklobdzija's collaborator, in fact, is a power-system specialist who has worked on power-system development for the space shuttle. "Maksimovic created a system that supplies power to the adiabatic logic and then recycles it," Oklobdzija said. Working together, "we have integrated both of those features on a single chip."
Medical devices are other potential applications. In hearing aids and pacemakers, for example, lowering the power consumption extends the products' usefulness. "Once a pacemaker is surgically implanted, you don't want to change the battery," Oklobdzija said. "With [current] pacemakers, they have to do surgery every couple of years to replace it." Any logic technique that reduces that need would be of value.
Oklobdzija would like to see the technology commercialized and is looking for industrial partners. "Given that we have fabricated and demonstrated the logic, we are very close to the phase where if someone wants to put it in production, they can do it," he said. "We have finished the R&D phase." -Additional reporting by Chappell Brown.
Copyright (c) 1997 CMP Media Inc.
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